Austin, Texas
FE Validation Engineer
We are looking for an experienced Verification Engineer to help develop a Gate Level Simulation methodology as a template for organizations across the company. You would work with top experts in the GLS, develop scalable GLS methodology and make significant contribution to the overall success of many upcoming ASICs that are key to the success of the company. You will learn and work on the most up to date methods to make GLS both easier, and more effective at finding the bugs that matter.
You will:
To be successful in the role you must have:
10 years of experience with a BSEE, or 7+ years with MSEE working at a senior level role in SOC/IP/ASIC design team with an emphasis on verification. Understanding of gate level cells and modeling required.
This role reports to the Head of DFX
What happens once you apply? To prepare yourself for the next steps, please explore here:
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